An integrated circuit can contain thousands of transistor devices on a single minute chip of semiconductor crystal because of the advanced miniaturization used in current semiconductor technology. But the limits imposed by conventional transistor structures and circuit geometry are quickly being approached. An object of this invention is to provide a transistor device having operating characteristics more favorable than those of any previously known devices which is particularly suitable for use in very high packing density integrated circuits. A further object of this invention is to provide a fabrication technique which allows for high density packing of transistor devices and their interconnections in integrated circuits.
A conventional bipolar transistor consists of a three layer pnp or npn semiconductor sandwich. These semiconductor layers form the emitter, base and collector of the device. In its operation, voltage bias is applied across the pn junctions at the interfaces of those layers through ohmic contacts made to each layer. Bipolar transistors are generally designed so that, when the emitter-base junction is forward biased, the current in the base is carried mostly by minority carriers (electrons or holes) which are injected from the emitter. Almost all of the injected current carriers pass through the base layer and are swept into the collector, forming the collector current (I.sub.c). The injected current at low current density is an exponential function of the bias voltage (V.sub.BE) applied to the emitter base junction so that the transconductance g.sub.m =(.differential.I.sub.c /.differential.V.sub.BE)/V.sub.CE =constant increases exponentially with voltage and becomes very large. Even at high injection levels the transconductance can increase with increasing injection but the increase is not as rapid as at low injection levels. A major advantage of the bipolar transistor is the very high transconductance that can be achieved for a given emitter-base junction area. A major limitation of the bipolar transistor is the time delay associated with the minority carrier transport in the base layer, which is responsible for charge storage delay. This delay presently limits the maximum frequency of oscillation of practical bipolar devices to approximately 20 GHz.
The metal base transistor is believed to have great potential because of its predicted high frequency performance. It is similar to the npn transistor except that the p layer is replaced by a metal to eliminate minority carrier charge storage in the base. The disadvantage of this device has been that the injected electrons experience considerable scattering as they pass through the metal layer. The result is a low ratio of collector current to emitter current .alpha., even though the transconductance g.sub.m can still be relatively high. The low .alpha. indicates low current gain and is a disadvantage in many applications, such as for example use in a digital computer circuit.
A metal gate transistor having high current gain was described by Joseph Lindmayer in the Proceeding of the IEEE, 1964, page 1751. In order to explain the high current gain of the device, the author postulated that the metal gate had random "weak points" through which the semiconductor layers are attached. However, the transconductance of the device g.sub.m was low. Presumably, the ratio g.sub.m /C.sub.be was also very low and the device was thus not appropriate for high frequency applications. A cutoff frequency of 10 MHz was reported.
In field effect transistors (FET) there is no minority carrier injection under normal operation. The device consists of a conducting channel made of semiconductor material with ohmic contacts at both ends. The channel passes near one or more electrodes or between two electrodes in such a way that voltage applied to the electrodes causes a modulation of the resistance of the channel. In an FET, as electrons or holes pass through the channel they do not pass over a barrier; rather, their potential always decreases as they move from source to drain. There are several types of FETs depending on the gate structure. The gate can be a pn junction (JFET), a Schottky barrier diode (MESFET) or a metal oxide semiconductor diode (MOSFET). Also, other configurations with gates buried in semiconductor material have been discussed in the literature, such as the gridistor and the analog transistor.
There are a number of modes for biasing FET devices. In all cases the transconductance is a function of the current in the channel, but is never as large, per unit of current, as is possible in a bipolar transistor. It is generally believed from calculation and experiments noted in the literature that the highest FET transconductance is achieved with a gate length which is several times larger than the channel thickness. Because there is no minority carrier injection with reverse gate bias, the maximum frequency of oscillation extends to 100 GHz and is limited by factors other than minority carrier injection.
The static induction transistor (SIT) is another three terminal device which can be used at microwave frequencies. The definition of this device is, at this writing, somewhat imprecise and in fact substantial overlap currently exists between what is labelled as SIT operation by some and FET operation by others. The SIT in its most common form includes a grid of p-type semiconductor material interposed between n-type source and drain regions. Voltage applied to the grid (or gate) controls the current flowing from the drain to the source. When the gate is negatively biased with respect to the source the control mechanism is the modulation of a potential barrier. When the gate is forward biased with respect to the source the control mechanism becomes a complicated combination of potential barrier modulation, conductance modulation and charge accumulation effects. These effects vary with device geometry and are largely responsible for the current semantic confusion connected with this device. Other versions of the SIT incorporate Schottky-barrier gate contacts fabricated on the same surface of the semiconductor as the source contact or fabricated in channels along side the source contact.
Although high frequency performance has been predicted for SIT devices, each version suffers from some disadvantage. In SIT's with p-type gate structures solid-state diffusion and series resistance limit the minimum dimensions achievable, which in turn limits the frequency of use to the low end of the microwave spectrum. Moreover, forward bias operation produces minority carrier injection and all of the associated deleterious time delay and diffusion capacitance effects. Other configurations in which gate structures are fabricated on the source surface of the device suffer a geometrical limitation in that it is impossible to make the channel thickness much smaller than the emitter contact width. This limitation limits the current handling capability of these structures and also increases the parasitic series source resistance.
A primary object of the present invention is to provide a transistor device which incorporates the advantages of all of the above devices while avoiding their disadvantages. The device of the present invention has available power gain even at very high frequencies in the order of 500 GHz. The transconductance of the device increases exponentially with base bias at low bias levels. The power-delay product for the transistor can be two orders of magnitude lower, that is better, than for the best equivalently sized FETs. The device also consumes a small surface area and lends itself to stacked transistor configurations to reduce the chip area required for each logic gate circuit. Because of its excellent high frequency performance, the device also has high potential in microwave systems. The device has lower noise than either the FET or the bipolar transistor.
As already noted, miniaturization of integrated circuits is limited by circuit geometry as well as by the individual devices. In virtually all large scale integrated circuits, interconnections between devices are formed along one surface of the semiconductor chip. These interconnections must be large enough to provide a low resistance path; they thus require a considerable surface area. Also, with all contacts to the transistors at the chip surface, the transistors themselves must be surface devices; and that is a major limitation to prior circuits.
A further object of this invention is to provide a fabrication technique and circuit elements which permit stacking of devices with a reduction in surface area requirements.